Texas Instruments 74LS14N Inverters are available at Mouser Electronics. Mouser offers inventory, pricing, & datasheets for Texas Instruments 74LS14N. The SN54LS/ 74LS13 and SN54LS / 74LS14 contain logic gates / inverters which accept standard TTL input signals and provide standard TTL output levels. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may.
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So on the 74LS14they tied Y1 to! E on the 74LS Why would they do this? Why not just tie the 74LS ‘s!
74LS14N datasheet, 74LS14N datasheets, manuals for 74LS14N electornic semiconductor part
E enable pin to ground? In fact, I can’t see why the Schmitt Inverter is used at all. The only other connections it has is A6 to external pin 26 on the dataseet and Y6 tied to A5 and Y5 tied to nothing. It just seems like a waste. Do you think it was used as some type of propagation delay? If so, seems like it would only be around 50ns or so.
Here is a crude schematic that I came up with. I might just try and dig up the real schematics to make sure I’m not crazy. Looks like I was wrong. A3 does indeed connect to Y5. Also, A2 is not floating, it is connected to GND.
It seems your circuit is incomplete or got pins mixed up. Datasheeg is extremely unlikely that outputs of the 74ls14 are used with the input being open.
As the 74ls14 is inverting, connecting two inverters in series to remove inversion is sensible and common. Thus it seems like you miss the A3 input. Finally while the delay is small, it might be sensible to make sure that the clock or enable signal arrives after some data signal or further control pins.
The propagation delay through two schmitt triggers might well be enough for that.
Your schematic is incomplete. There is at least one connection you’ve missed, which is Y5. I suspect it connects to A3. You might want to check continuity. In any event, the external Pin 26 provides a signal which is used to 74le14n the card act as an auxiliary memory. The input is active low, and the LS is active low, so using 4 LS14 gates will provide signal buffering as well as a reasonable delay nominally about 60 nsec.
Since this is board-level enable line, I’d guess that the delay is irrelevant. More likely, I 74lls14n, is that using 4 gates rather than the 2 which would make sense when seen from the datassheet of view of buffering, may well be driven by pcb routing considerations.
TTL floating inputs inputs default high, so A3 high dtaasheet make 74le14n and A1 low, which will make Y1 permanently high, permanently disabling the ‘ There’s obviously something happening at A3 that you missed, so you need to backtrack and reverse-engineer a little deeper.
Why would a 74LS14 be used to enable another IC? Anyway, I’m sure the schematic is online somewhere but I just wanted to do this for fun. Michael Karcher 1, 3 9. It was common back in the days when this kind of design was being done to use gate delays to control the sequencing of data sources onto a 74,s14n, fine-tuning the enabling and disabling of different 774ls14n to insure that they wouldn’t “fight” each other, while still meeting setup and hold times on the actual data transfers.
I’ll check the continuity later on like I mentioned in a comment below. But, visually at least, it appeared that A3 was floating. The bottom IC is incomplete in my drawing above because I was only concerned with the! However, the top IC appears to be complete in my drawing above. Again, based on a purely un-scientific visual inspection. A small propagation delay would make sense to me.
Do you have more info on what that is and how it affects circuits? In an ideal circuit, a signal that changes from high to low goes low at all inputs pins exactly datashret the point in time the output gets driven low.
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In a real circuit, pulling a signal low means discharging its capacitance, which is hindered by the inductance of the traces. So even if one manages to do a hard step at the output creating a signal, the step will 74ls14m distorted at input pins mostly the step will be washed outand in case of splitting traces without proper termination, you can even get dxtasheet and get very funny curve shapes from high to low or low to high A schmitt-trigger device is made to deal especially with the false detection of multiple edges by adding hysteresis – i.
Thank you for that explanation. I’m just recently learning a little more about hysteresis in general. But you’re also saying, that an ideal circuit should also never have floating pins? Granted, I’m sure many a product has been made floating but it isn’t ideal. WhatRoughBeast 49k datasueet 28 A good idea on checking continuity. I was only checking visually with a magnifying glass.
I was pretty sure Y5 and A3 went nowhere but I will do a continuity check later and see.
So you’re saying that you think it’s used for signal buffering? And, because of the way the Apple IIe was designed routedthe extra delay might have been needed? A trace from Y5 to A3 will almost certainly be entirely under the IC on the top layer, so you can’t see it. And when I say routing, I mean physical routing, actually laying out the traces so that you can connect pin A to pin B.
And I doubt the delay is important, but I don’t know enough about the motherboard function to be sure. That was spot on. datasheett
Motorola – datasheet pdf
Yes, Y5 is connected to A3. I checked it with a continuity tester and sure enough, they are connected. Which I assumed would be LOW. The other pins floating came up around 0. Leading me to assume floating pins were default LOW. On 74HCxxx High-speed CMOS daasheet, unconnected datashest are undefined, and can provide either level, or even pick up radio signals or signals from neighbouring traces.
Your question’s illustration showed 74LS as the logic family you were using, in which inputs default to high if they’re left floating. Ah, thank you both. I didn’t know that about HC components. I knew that my HC wasn’t exactly like the LS used on the actual circuit dataaheet knowing that difference makes sense. Also shows me I can’t always assume any results without knowing ALL of the parameters.
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